Current mode logic (CML) circuit blocks are commonly used in semiconductor integrated circuit designs because of the various advantages of CML circuit blocks. However, conventional CML circuit blocks generally lack a mechanism to restrain the output differential signal Direct Current (DC) levels when running close to the edge of the bandwidth of the CML circuit blocks. With slightly non-ideal inputs (such as a delay offset) or mismatched devices in the CML circuit blocks, the positive and negative output DC levels may drift away from each other, causing significant output duty cycle distortion. The output duty cycle distortion is especially serious through a series of CML buffers through which the effect accumulates.
FIG. 1 shows a conventional Vss-referenced (also referred to as ground-referenced) complementary metal oxide semiconductor (CMOS) CML buffer with active loads. The CML buffer 100 is a differential-input differential-output logic circuit that provides high-speed operation and good power supply noise rejection (PSNR). The CML buffer 100 includes a current source 110 to deliver a substantially fixed current I, which may be wholly or partly steered to one of the two active loads 121 and 122 via the differential pair of Metal Oxide Semiconductor Field Effect Transistors (MOSFET) 131 and 132. The differential nature of the CML buffer 100 and the substantially fixed supply current I make the CML buffer 100 more resistant to power supply noise. Furthermore, the reduced output voltage swing may allow the CML buffer 100 to operate at a higher frequency than other types of conventional CMOS logic circuits.
However, the output cycle distortion of the CML buffer 100 may limit the operation frequency of the CML buffer 100. One reason the output cycle distortion occurs is that the CML buffer 100 CMOS devices run out of bandwidth at high frequencies, making the CML buffer 100 unable to generate a full-swing CML output. Since the output load cannot be fully charged or discharged to the intended swing limited voltage levels within the signal period, mismatches in the input signal and the circuit components generate DC level mismatch on the CML buffer 100 differential outputs. This problem worsens as the differential signals propagate through a series of CML buffers.
In one conventional CML path, which includes a six-stage CML buffer chain and multiple multiplexers, the output experienced large duty cycle distortion at high frequencies (e.g., approximately 800 MHz or above). FIG. 2 shows the waveforms generated from the conventional CML path simulation. The conventional CML path was simulated in a slow corner with slightly non-ideal differential inputs having a duty cycle of about 49%. The differential input waveforms 210 are shown in the upper half of FIG. 2. The differential output waveforms 220 of the CML path reveal a duty cycle of about 45.5%, which corresponds to about 3.5% duty cycle distortion, with considerable DC mismatch between the outputs. The duty cycle distortion further increases when random device mismatches, such as CMOS device threshold voltage (Vt) mismatch, are introduced.